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(R)
AS4LC8M8S0 AS4LC4M16S0
3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
Features
* PC100/133 compliant * Organization - 2,097,152 words x 8 bits x 4 banks (8Mx8) - 1,048,576 words x 16 bits x 4 banks (4Mx16) * Fully synchronous - All signals referenced to positive edge of clock * Four internal banks controlled by BA0/BA1 (bank select) * High speed - 133/125/100 MHz - 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time * Low power consumption - Standby: 7.2 mW max, CMOS I/O
* 4096 refresh cycles, 64 ms refresh interval * Auto refresh and self refresh * Automatic and direct precharge * Burst read, single write operation * Can assert random column address in every cycle * LVTTL compatible I/O * 3.3V power supply * JEDEC standard package, pinout and function - 400 mil, 54-pin TSOP II * Read/write data masking * Programmable burst length (1/2/4/8/full page) * Programmable burst sequence (sequential/interleaved) * Programmable CAS latency (2/3)
Pin arrangement
AS4LC4M16S0
VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
Pin designation
Pin(s) DQM (8Mx8) UDQM/LDQM (4Mx16) A0 to A11 BA0, BA1 DQ0 to DQ7 (8Mx8) DQ0 to DQ15 (4Mx16) RAS CAS WE CS VCC, VCCQ VSS, VSSQ CLK CKE Description Output disable/write mask Address inputs Bank select inputs Input/output Row address strobe Column address strobe Write enable Chip select Power (3.3V 0.3V) Ground Clock input Clock enable
AS4LC4M16S0
Selection guide
Symbol Bus frequency Minimum clock access time Minimum setup time Minimum hold time Minimum RAS to CAS delay Minimum RAS precharge time Remarks: (CL/tRCD/tRP) CL = 2 CL = 3 fmax tAC tAC tS tH tRCD tRP -75 (PC133) 133 - 5.4 1.5 0.8 3 3 3/3/3 -8 125 - 6 2 1.0 3 3 3/3/3 -10F (PC100) 100 6 - 2 1.0 2 2 2/2/2 -10 (PC100) 100 - 6 2 1.0 3 3 3/3/3 Unit MHz ns ns ns ns cycles cycles
54-pin TSOP
4LC4M16S0
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Copyright (c)2000 Alliance Semiconductor. All rights reserved.
AS4LC4M16S0 AS4LC16M4S0
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Functional description
The AS4LC8M8S0 and AS4LC4M16S0 are high-performance 64-megabit CMOS Synchronous Dynamic Random Access Memory (SDRAM) devices organized as 2,097,152 words x 8 bits x 4 banks, and 1,048,576 words x 16 bits x 4 banks, respectively. Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock. Programmable burst mode can be used to read up to a full page of data without selecting a new column address. The four internal banks can be alternately accessed (read or write) at the maximum clock frequency for seamless interleaving operations. This provides a significant advantage over asynchronous EDO and fast page mode devices. This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type (sequential or interleaved). Lower latency improves first data access in terms of CLK cycles, while higher latency improves maximum frequency of operation. This feature enables flexible performance optimization for a variety of applications. DRAM commands and functions are decoded from control inputs. Basic commands are as follows: * Deactivate all banks * Select row; activate bank * Mode register set * Deactivate bank * Deselect; power down * CBR refresh * Select column; write * Select column; read
* Auto precharge with read/write * Self-refresh
The 64 Mb DRAM devices are available in 400-mil plastic TSOP II packages and have 54 pins in each configuration. Both devices operate with a power supply of 3.3V 0.3V Multiple power and ground pins are provided for low switching noise . and EMI. Inputs and outputs are LVTTL-compatible.
Logic block diagram
CLK Clock generator CKE BA0, BA1 A[11:0] Bank select Row address buffer Mode register Refresh counter
Command decoder
CS RAS CAS WE
Control logic
Burst counter
Data control circuit
Input and output buffer
Latch circuit
Column address buffer
Bank A 1Mx16 (4096x256x16) Bank B 1Mx16 (4096x256x16) Bank C 1Mx16 (4096x256x16) Bank D 1Mx16 (4096x256x16) Sense amplifier Column decoder and latch circuit
Row decoder
DQM
DQ
For AS4LC8M8S0, Banks A-D will read 8Mx8 (4096x512x8). For AS4LC4M16S0, DQM will be UDQM and LDQM.
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Pin descriptions
Pin CLK Name System clock Description All operations synchronized to rising edge of CLK. It also increments the burst counters. Controls CLK input. If CKE is high, the next CLK rising edge is valid. If CKE is low, the internal clock is suspended from the next clock cycle and the burst address and output states are frozen. Pulling CKE low has the following effects: all banks idle: Precharge power down and Self refresh. row active in any bank: Active power down. burst/access in progress: Clock suspend. When in Power down or Self refresh mode, CKE becomes asynchronous until exiting the mode. CS A0~A11 Chip select Address Enables or disables device operation by masking or enabling all inputs except CLK, CKE, UDQM/LDQM (x16), DQM (x8). Row and column addresses are multiplexed. Row address: A0~A11. Column address (8Mx8): A0~A8. Column address (4Mx16): A0~A7. Memory cell array is organized in 4 banks. BA0 and BA1 select which internal bank will be active during activate, read, write, and precharge operations. Enables row access and precharge operation. When RAS is low, row address is latched at the rising edge of CLK. Enables column access. When CAS is low, starting column address for the burst access operation is latched at the rising edge of the CLK. Enables write operation and row precharge operation.
CKE
Clock enable
BA0, BA1 RAS CAS WE
Bank select Row address strobe Column address strobe Write enable
x8: DQM x16: UDQM/LDQM
Controls I/O buffers. When DQM is high, output buffers are disabled during a read operation and input data is masked during a write operation. DQM latency is 2 clocks for Read and 0 clocks for Write. Output disable/ write For x16, LDQM controls lower byte (DQ0-7) and UDQM controls mask upper byte (DQ8-15). For x8, only one DQM controls the 8 DQs. UDQM and LDQM are considered same state when referenced as DQM. Data input/output Data inputs/outputs are multiplexed. Data bus for 8Mx8 is DQ0~DQ7 only.
DQ0~DQ15 VDD/VSS VDDQ/VSSQ
Power supply/ground Power and ground for core logic and input buffers. Data output power/ ground Power and ground for data output buffers.
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Commands
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit CKEn-1 CKEn H* H H L H H H H Selected bank All banks H H L H L H H L H H H H H H L H L H CS L L L L H L L L L L H L X H L H L X H H RAS L L L H X L H H H L X V X X H X V X CAS L L L H X H L L H H X V X X H X V X WE L H H H X H H L L L X V X X H X V X H X X X X 7 X X X X X X X X X X DQM X X X X X X X X X X V X - - - - V V V L H L H X L H X X BA0/ BA1 A10 A9-A0 - - - - row address column address column address X X Valid Active X 4 4,5 4 4,5 6 4 X DQ X Note 1,2 3 3 3 3
Op code
Bank activate Read Write Burst stop Precharge Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
Clock suspend or Entry active power down Exit Entry Precharge power down mode Exit Write enable/output enable Write inhibit/Output High-Z
DQM
No operation command
H
X
H L
X H
X H
X H
X X
X
X
X
X
1 2 3 4
5 6 7
OP = operation code. A0~A11 and BA0~BA1 program keys. MRS can be issued only when all banks are precharged. A new command can be issued 1 clock cycle after MRS. Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic. Auto/self refresh can only be issued after all banks are precharged. BA0~BA1: bank select addresses. If A10/AP is High at row precharge, BA0 and BA1 are ignored and all banks are selected. During read, write, row active, and prechage: If BA0 and BA1 are Low, Bank A is selected. If BA0 = Low and BA1 = High, Bank B is selected. If BA0 = High and BA1 = Low, Bank C is selected. If BA0 and BA1 are High, Bank D is selected. A new read/write command to the same bank cannot be issued during a burst read/write with auto precharge. A new row active command can be issued after t(t RP/tCK + BL +) cycles. Burst stop command valid at every burst length. DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0). Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2).
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AS4LC8M8S0 AS4LC4M16S0
Mode register fields
Register programmed with MRS Address Function
RFU = 0 during MRS cycle.
A11~A10 RFU
A9 WBL
A8 TM
A7
A6
A5 CAS latency
A4
A3 BT
A2
A1
A0
Burst length
Write burst length A9 0 Length Programmed burst length Single burst A3 0 1
Burst type Type Sequential Interleaved
1
Test mode A8 0 0 1
1
A7 0 1 0 1
Type Mode register set Reserved Reserved Reserved
CAS latency A6 0 0 0 0 1 A5 0 0 1 1 X A4 0 1 0 1 X Latency Reserved Reserved 2 3 Reserved A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1
Burst length A0 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 Reserved Reserved Reserved Full page BT = 1 1 2 4 8 Reserved Reserved Reserved Reserved
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Recommended operating conditions
Parameter Supply voltage Input voltage Output voltage Input leakage current Any input 0V VIN VCC Output leakage current DQs are disabled 0V VOUT VCCQ Ambient operating temperature
V min = -1.5V for pulse widths less than 5 ns. IL I OH = -2mA, and I OL = 2mA.
Symbol VCC,VCCQ GND VIH VIL VOH VOL IL IOZ TA
Min 3.0 0.0 2.0 -0.3 2.4 - -5 -5 0
Max 3.6 0.0 VCC + 0.3 0.8 - 0.4 +5 +5 70
Unit V V V V V V uA uA C
Recommended operating conditions apply throughout this document unless otherwise specified.
Absolute maximum ratings
Parameter Input voltage Power supply voltage Storage temperature (plastic) Power dissipation Short circuit output current Symbol VIN,VOUT VCC,VCCQ TSTG PD IOUT Min -1.0 -1.0 -55 - - Max +4.6 +4.6 +150 1 50 Unit V V
C
W mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance
Parameter Input capacitance: CLK Input capacitance: All other input-only pins Input/output capacitance Symbol Ci1 Ci2 CI/O Min 2.5 2.5 4.0 Max 4 5 6.5 Unit pF pF pF Notes 1, 2, 3 1, 2, 4 1, 2, 5
Notes 1 This parameter is sampled. VCC = VCCQ = 3.3V; f = 1MHz; TA = 23 C; pin under test biased at 1.4V. 2 Max value is specified for -10, -10F, and -8. 3 For -75 part, Max = 3.5 pF. 4 For -75 part, Max = 3.8 pF. 5 For -75 part, Max = 6.0 pF.
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AS4LC8M8S0 AS4LC4M16S0
IDD specifications and conditions (0 C TA 70 C, VDD, VDDQ = +3.3V 0.3V)
Max Parameter Operating current: active mode; burst = 2; READ or WRITE; tRC = tRC(min); CAS latency = 3 Standby current: power-down mode; all banks idle; CKE = low Standby current: active mode; CKE = high; CS# = high; all banks active after tRCD met; no accesses in progress Operating current: burst mode; continuous burst; READ or WRITE; all banks active; CAS latency = 3 Auto refresh current: CKE = high; CS# = high Self-refresh current: CKE 0.2V tRFC = tRFC(min); CL = 3 tRFC = 15.625ms; CL = 3 Symbol IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 -75 115 2 45 140 210 50 1 -8 95 2 35 130 210 50 1 -10F/10 95 2 35 120 190 40 1 Units mA mA mA mA mA mA mA Notes 4, 5 4,5 4, 5 4,5 4, 5 4,5 4,5
Notes 1 IDD specifications are tested after proper initialization of the device. 2 IDD is dependent on output loading and clock cycle time. Values are specified with minimum cycle time and outputs open. 3 IDD tests have VIL = 0V and V IH = 3V. 4 IDD current will decrease at lower CAS latencies. This is because the lower the latency, the lower the clock cycle time. 5 Address transitions average one transition every two clock cycles.
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AC parameters common to all waveforms
Sym Parameter -75 CAS latency Min Max 15 20 20 44 66 1 2 1 1 3 2 3 2 3 2 7.5 10 5.4 6 2.7 3 2.5 2.5 1.5 0.8 1 3 2 - - 0.8 1.5 0.8 1.5 0.8 1.5 - - - - - - - - - - - - - - - - - - - - 6 6 - - - - - - -8 Min 20 20 20 50 70 1 2 1 1 8 10 6 6 3 3 3 3 2 1 1 - - 1 2 1 2 1 2 Max - - - - - - - - - - - - - - - - - - - - 7 7 - - - - - - 20 20 20 50 70 1 2 1 1 10 15 6 6 3 3 3 3 2 1 1 - - 1 2 1 2 1 2 -10F Min Max - - - - - - - - - - - - - - - - - - - - 7 7 - - - - - - Min 20 30 30 60 90 1 2 1 1 10 15 6 6 3 3 3 3 2 1 1 - - 1 2 1 2 1 2 -10 Max - - - - - - - - - - - - - - - - - - - - 7 7 - - - - - - Unit Notes ns ns ns ns ns CLK CLK CLK CLK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 2 2 2 3 4 4 4,5,7 4,5,7 4,5,7 4,5,7 6 6 6 6 5
tRRD Row active to row active delay tRCD RAS to CAS delay time tRP Row precharge tRAS Row active tRC Row cycle time tCDL Last data in to new column address delay
tRDL Last data in to row precharge tBDL Last data in to burst stop tCCD Column address to column address delay
tCK CLK cycle time tAC CLK to valid output delay @ 50pF tOH Output data hold time @ 50 pF tCH CLK high pulse width tCL CLK low pulse width tAS Add setup time tAH Add hold time tSLZ CLK to output in low Z tSHZ CLK to output in high Z tCKH CKE hold time tCKS CKE setup time tCMH tCMS CS, RAS, CAS, WE, DQM hold time CS, RAS, CAS, WE, DQM setup time
tDH Data in hold time tDS Data in setup time
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AS4LC8M8S0 AS4LC4M16S0
AC parameters common to all waveforms (continued)
Sym tDQD Parameter DQM to input data delay DQM to data high Z during reads Write command to input data delay Data-in to active command Load mode register to active/ refresh command Data-out high Z from precharge/burst stop command CKE to CLOCK disable or powerdown entry mode CKE to clock enable or powerdown exit mode 3 2 -75 CAS latency Min Max 1 0 2 0 5 1 3 2 1 1 - - - - - - - - - - -8 Min 1 0 2 0 5 1 3 2 1 1 Max - - - - - - - - - - 1 0 2 0 5 1 3 2 1 1 -10 F Min Max - - - - - - - - - - Min 1 0 2 0 5 1 3 2 1 1 -10 Max - - - - - - - - - - Unit CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK 4 4 Notes
tDQM DQM to data mast during writes tDQZ tDWD tDAL tMRD tROH tCKED tPED
Notes 1 Minimum clock cycles = (Minimum time / clock cycle time) rounded up. 2 Minimum delay required to complete write. 3 Column address change allowed every cycle. 4 Parameters dependent on CAS latency. 5 If clock rising time > 1ns, (tr/2-0.5)ns should be added to parameter. 6 If (tr and tf) > 1ns, [(tr+tf)/2-1]ns should be added to parameter. 7 Outputs measured at 1.5V with 50pF load only without resistive termination.
Burst sequence
Initial address A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 Sequential 1 2 2 3 3 0 0 1 Interleave 3 0 1 2 0 1 2 3 1 0 3 2 2 3 0 1
(BL = 4)
3 2 1 0
Burst sequence
A2 0 0 0 0 1 1 1 1 Initial address A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Sequential 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 Interleave 3 4 2 5 1 6 0 7 7 0 6 1 5 2 4 3
(BL = 8)
0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0
2 3 4 5 6 7 0 1
5 6 7 0 1 2 3 4
6 7 0 1 2 3 4 5
7 0 1 2 3 4 5 6
0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1 0
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AS4LC4M16S0 AS4LC16M4S0
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Device operation
Command Pin settings Description The following sequence must be performed prior to normal operation. 1. Apply power, start clock, and assert CKE and DQM high. All other signals are NOP. 2. After power-up, pause for a minimum of 200s. CKE/DQM = high; all others NOP. 3. Precharge both banks. 4. Perform Mode Register Set command to initialize mode register. 5. Perform a minimum of 8 auto refresh cycles to stabilize internal circuitry. (Steps 4 and 5 may be interchanged.) The mode register stores the user selected opcode for the SDRAM operating modes. The CAS latency, burst length, burst type, test mode and other vendor specific functions are selected/programmed during CS = RAS = CAS = WE = low; the Mode Register Set command cycle. The default setting of the A0~A11 = opcode mode register is not defined after power-up. The power-up and mode register set cycle must be executed prior to normal SDRAM operation. Refer to the Mode Register Set table and timing for details. The SDRAM performs a "no operation" (NOP) when RAS, CAS, and WE = high. Since the NOP performs no operation, it may be used as a wait state in performing normal SDRAM functions. The SDRAM is deselected when CS is high. CS high disables the command decoder such that RAS, CAS, WE and address inputs are ignored. Device deselection is also considered a NOP.
Power up
Mode register set
Device deselect and no operation
CS = high
Bank activation
The SDRAM is configured with four internal banks. Use the Bank CS = RAS = low; CAS = WE = Activate command to select a row in one of the idle banks. Initiate high; A0~A10 = row address; a read or write operation after tRCD(min) from the time of bank BA0~BA1 = bank select activation. CS = CAS = A10 = low; RAS = WE = high; BA0~BA1 = bank select, A0~A8 = column address; (A9 = don't care for 8Mx8; A8,A9 = don't care for 4Mx16) Use the Burst Read command to access a consecutive burst of data from an active row in an active bank. Burst read can be initiated on any column address of an active row. The burst length, sequence and latency are determined by the mode register setting. The first output data appears after the CAS latency from the read command. The output goes into a high impedance state at the end of the burst (BL = 1,2,4,8) unless a new burst read is initiated to form a gapless output data stream. Terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write. Use the Burst Write command to write data into the SDRAM on consecutive clock cycles to adjacent column addresses. The burst length and addressing mode is determined by the mode register opcode. Input the initial write address in the same clock cycle as the Burst Write command. Terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write. Use DQM to mask input and output data on a cycle-by-cycle basis. It disables the output buffers in a read operation and masks input data in a write operation. The output data is invalid 2 clocks after DQM assertion (2 clock latency). Input data is masked on the same clock as DQM assertion (0 clock latency).
Burst read
Burst write
CS = CAS = WE = A10 = low; RAS = high; A0~A9 = column address; (A9 = don't care for 8Mx8; A8,A9 = don't care for 4Mx16)
UDQM/LDQM (x16), DQM (x8) operation
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AS4LC8M8S0 AS4LC4M16S0
Device operation (continued)
Pin Settings Description CS = WE = low; RAS = Use burst stop to terminate burst operation. This command may be used Burst stop to terminate all legal burst lengths. CAS = high The Bank Precharge command precharges the bank specified by BA0 and CS = A10 = RAS = WE = BA1. The precharged bank is switched from active to idle state and is low; CAS = high; A11 = Bank precharge ready to be activated again. Assert the precharge command after bank select; A0~A9 = tRAS(min) of the bank activate command in the specified bank. The don't care precharge operation requires a time of tRP(min) to complete. CS = RAS = WE = low; The Precharge All command precharges all four banks simultaneously. CAS = A10 = high; Precharge all BA0~BA1 = bank select; All four banks are switched to the idle state on precharge completion. A0~A9 = don't care CS = CAS = WE (write) = During auto precharge, the SDRAM adjusts internal timing to satisfy low; RAS = WE (read) = tRAS(min) and tRP for the programmed CAS latency and burst length. A10 = high; BA0~BA1 = Couple the auto precharge with a burst read/write operation by bank select; A0~A9 = asserting A10 to a high state at the same time the burst read/write Auto precharge column address; (A9 = commands are issued. At auto precharge completion, the specified bank don't care for 2Mx8; is switched from active to idle state. Note that no new commands to the A8,A9 = don't care for bank can be issued until the specified bank achieves the idle state. Auto 1Mx16) precharge doesn't work with full-page burst. When CKE is low, the internal clock is frozen or suspended from the next clock cycle and the state of the output and burst address are frozen. Clock suspend/power If all banks are idle and CKE goes low, the SDRAM enters power down CKE = low down mode entry mode at the next clock cycle. When in power down mode, no input commands are acknowledged as long as CKE remains low. To exit power down mode, raise CKE high before the rising edge of CLK. Resume internal clock operation by asserting CKE high before the rising Clock suspend/power CKE = high edge of CLK. Subsequent commands can be issued one clock cycle after down mode exit the end of the Exit command. SDRAM storage cells must be refreshed every 64ms to maintain data integrity. Use the Auto Refresh command to refresh all rows in all banks of the SDRAM. The row address is provided by an internal counter which increments automatically. Auto refresh can only be asserted when CS = RAS = CAS = low; all four banks are idle and the device is not in the power down mode. WE = CKE = high; Auto refresh The time required to complete the auto refresh operation is tRC(min). A0~A11 = don't care Use NOPs in the interim until the auto refresh operation is complete. This is the most common refresh mode. It is typically performed once every 15.6us or in a burst of 4096 auto refresh cycles every 64ms. All four banks will be in the idle state after this operation. Self refresh is another mode for refreshing SDRAM cells. In this mode, refresh address and timing are provided internally. Self refresh entry is allowed only when all four banks are idle. The internal clock and all CS = RAS = CAS = CKE = input buffers with the exception of CKE are disabled in this mode. Exit low; WE = high; A0~A11 self refresh by restarting the external clock and then asserting CKE high. Self refresh = don't care NOP's must follow for a time of tRC(min) for the SDRAM to reach the idle state where normal operation is allowed. If burst auto refresh is used in normal operation, burst 4096 auto refresh cycles immediately after exiting self refresh. Command
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Mode register set command waveform
CLK CMD PRE tRP
MRS can be issued only when both banks are idle.
MRS tRSC(min)
ACT
Precharge waveforms
Precharge can be asserted after tRAS (min). The selected bank will enter the idle state after tRP.. The earliest assertion of the precharge command without losing any burst data is show below.
(normal write; BL = 4)
CLK CMD DQ WE D0 D1 D2 D3 PRE
(normal read; BL = 4)
CLK CMD DQ(CL2) DQ(CL3) Read data Q0 Q1 Q0 PRE Q2 Q1 Q3 Q2 Q3
Auto precharge waveforms
A10 controls the selection of auto precharge during the read or write command cycle.
(write with auto precharge; BL = 4)
CLK CMD DQ WE D0 D1 D2 D3 Auto precharge starts*
(read with auto precharge; BL = 4)
CLK CMD DQ(CL2) DQ(CL3) Read data Q0 Q1 Q0 Q2 Q1 Q3 Q2 Q3
Auto precharge starts*
* The row active command of the precharge bank can be issued after t from this point. At burst read/write with auto precharge, CAS interrupt of the same RP
bank is illegal; other bank is described below.
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Concurrent Auto-P Waveforms
According to IntelTM's specification, auto-p burst interruption is allowed by another burst provided that the interrupting burst is in a different bank than the ongoing burst.
(A) RD-P interrupted by RD in another bank (CL = 3, BL = 4)
CLK CMD DQ
RD-P (A) RD (B)
A0
A1
B0
B1
B2
B3
Bank A Precharge Starts *
(B) RD-P interrupted by WR in another bank (CL = 2, BL = 8)
CLK CMD DQM DQ QA0 QA1 DN(B0) D(B1) D(B2) D(B7)
RD-P (A) WR (B)
Bank A Precharge Starts *
(C) WR-P interrupted by RD in another bank (CL = 2, BL = 4)
CLK CMD DQ
WRP (A) RD (B)
D(A0)
D(A1)
QB0
QB1
QB2
QB3
Bank A Precharge Starts *
* The row active command of the precharge bank can be issued after t RP from this point.
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(D) WR-P Interrupted by WR in another bank (CL = 3, BL = 4)
CLK CMD
WRP (A) WR (B)
DQ
DA0
DA1
DA2
DB0
DB 1
DB2
DB3
Bank A Precharge Starts *
* The row active command of the precharged bank can be issued after t from this point. RP
Clock suspension read waveforms
CLK external CLK internal CKE DQM DQ Q1 Q2 Q3 Q4 OPEN OPEN Q6
(BL = 8)
CLK external CLK internal CKE DQM DQ Q1 Q2 Q3 Q4 OPEN CLK external CLK internal CKE DQM DQ Q1 Q2 Q3 Q4 Q5 Q6 Q6
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AS4LC8M8S0 AS4LC4M16S0
(BL = 8)
Clock suspension write waveforms
CLK external CLK internal CKE DQM DQ D1 D2 D3 DQM Mask CLK external CLK internal CKE DQM DQ D1 D2 D3 DQM Mask CLK external CLK internal CKE DQM DQ D1 D2 D3 D4 D5 D6 CKE Mask D5 D6 D5 CKE Mask D6
Read/write interrupt timing
CLK CMD ADD DQ (CL2) DQ (CL3)
tCCD = CAS to CAS delay (= 1 CLK)
read interrupted by read (CL = 2, BL = 4)
Read data A
Read data B QA0 QB0 QA 0 QB 1 QB 0 QB2 QB1 QB 3 QB2 QB3
tCCD
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15
AS4LC4M16S0 AS4LC16M4S0
(R)
write interrupted by write (BL = 4)
CLK CMD ADD DQ tCCD Write data Write data A0 DA0 tCDL B0 DB 0 DB 1 DB 2 DB3
tCCD = CAS to CAS delay (= 1 CLK) tCDL = last address in to new column addres delay (= 1 CLK)
write interrupted by read (CL = 2, BL = 4)
CLK CMD ADD DQ (CL2) DQ (CL3) tCCD Write data Read data A DA0 DA0 tCDL
tCCD = CAS to CAS delay (= 1 CLK) tCDL = last address in to new column addres delay (= 1 CLK)
B QB0 QB 1 QB0 QB 2 QB 1 QB3 QB2 QB 3
read interrupted by write (CL = 3, BL = 4)
CLK CMD DQM DQ
* To prevent bus contention, maintain a gap between data in and data out.
Read data
Write data*
Q0
D0
D1
D2
D3
Burst termination
Burst operations may be terminated with a Read, Write, Burst Stop, or Precharge command. When Burst Stop is asserted during the read cycle, burst read data is terminated and the data bus goes to High Z after CAS latency. When Burst Stop is asserted during the write cycle, burst write data is terminated and the databus goes to High Z simultaneously.
Burst stop command waveform, read cycle
CLK CMD DQ (CL = 2) DQ (CL = 3) Read data Q0 Burst stop Q1 Q0 Q2 Q1 Q2
(BL = 8)
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ALLIANCE SEMICONDUCTOR
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(R)
AS4LC8M8S0 AS4LC4M16S0
write cycle
CLK CMD DQ (CL = 2,3) Write data Q0 Q1 Q2 Q3 Burst stop
Precharge command
A Precharge command can be used to interrupt burst read/write operation during the read cycle. During RD, burst read is terminated and o/p goes to High Z after CAS latency. The same bank can be activated after tRP . During write, burst write operation is terminated immediately. Data written two cycles prior to the precharge command will be correctly stored. Set DQM high one cycle before Precharge command and hold it high until Precharge command to mask and avoid writing invalid data.
read cycle (CL = 2)
CLK CMD DQ Read data Q0 Q1 PRE Q2 Q3 tRP ACT
read cycle (CL = 3)
CLK CMD DQ Read data Q0 PRE Q1 Q2 Q3 ACT
write cycle (BL = 8)
CLK CMD DQ DQM Write data D0 D1 D2 D3 Masked PRE Q4 tRP ACT
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17
AS4LC4M16S0 AS4LC16M4S0
(R)
Auto refresh waveform
CLK
tRP tRC tRC
CS RAS CAS WE BA0/BA1 A10 A0-A9 DQM CKE DQ Precharge all banks Auto refresh Auto refresh Auto refresh
If A10 = High, then BA0/BA1 = don't care; if A10 = low, then BA0/BA1 = bank select. Banks
Self refresh waveform
CLK CS RAS CAS WE BA0/BA1 A10 A0-A9,A11 DQM CKE DQ Precharge all banks Self refresh entry
Self refresh cycle tRC RAa RAa
Self refresh exit
Arbitrary cycle
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(R)
AS4LC8M8S0 AS4LC4M16S0
Power down mode waveform
CLK CS RAS CAS WE BA0/BA1 A10 A0-A9,A11 DQM CKE DQ Bank activate
Power down mode entry Active standby Power down mode Power down mode exit Power down mode entry NOP Precharge standby Power down mode NOP RAa RAa RAa
CAa
RAa
CAx
Bank activate
Power down mode exit
Enter power down mode by pulling CKE low. All input/output buffers (except CKE buffer are turned off in power down mode. When CKE goes high, command input must be equal to no operation at next CLK rising edge.
Read/write waveform
CLK CS RAS CAS WE BA0/BA1 A10 A0-A9,A11 DQM CKE DQ Bank activate
Read Aa 0 Q Aa 1 Q Aa 2 Q Aa 3 Q Aa 4 Q Aa 5 Q Ab0 D Write Ab1 D Ab 2 D Ab 3 D Ab 4 D Ab 5 D tRP tRP RAa CAa CAb tRAS
(BL = 8, CL = 3)
tRP
RAb
RAa
RAb
Bank activate
Precharge
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19
AS4LC4M16S0 AS4LC16M4S0
(R)
Burst read/single write waveform
CLK CS RAS CAS WE BA0/BA1 A10 A0-A9,A11 DQM CKE DQ Activate Read
Aa0 Q Aa1 Q Aa2 Q Aa3 Q D Aa4 Single Write D Aa5 Ad0 Q RAa CAr CAd
(BL = 4, CL = 3)
RAa
CAa
CAb
Ad1 Q
Ad2 Q
Ad3 Q
Read
Interleaved bank read waveform
CLK
tCCD tCCD tCCD tRP
(BL = 4, CL = 3)
CS
tRAS
RAS CAS WE BA0/BA1 A10 A0-A9, A11 DQM CKE DQ Bank A Bank B Active Read Read
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QAb0 QAb1 QAb2 QAc0 QAc1 QAc2 QBb0 QB b1 QB b2 QBb3 Bank tRCD RAa RBa CAa RBa CBa CAb CAc CBb Bank Bank tRCD Bank Bank Bank Bank Bank Bank
RAa
Read Read
Precharge Precharge
BA0 and BA1 together determine which bank undergoes operations.
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ALLIANCE SEMICONDUCTOR
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(R)
AS4LC8M8S0 AS4LC4M16S0
(BL = 4, CL = 3, Autoprecharge)
Interleaved bank read waveform
CLK CS
tRC
tRC tRC tRC
RAS
tRAS tRP tRAS
tRAS tRP
tRP tRAS
tRAS
CAS WE BA0/BA1 A0-A9, A11 A10 DQM CKE
tRRD tRRD Bank tRCD RAa RAb Bank Bank tRCD Bank
Bank
Bank tRCD RAc RAc
Bank
Bank tRCD RAd
Bank
RAe
RAa
CAa
RAb
CBb
CBc
RAd
CBd
RAe
tRRD QB b0 QBb1 QBb2 QB b3
tRRD QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2
DQ Bank A Bank B Active Read Active
QAa0 QAa1 QAa2 QAa3
AP
Active Read
Read AP Active
AP Read
Active
BA0 and BA1 together determine which bank undergoes operations. AP = internal precharge begins.
Interleaved bank read waveform
CLK CS
tRC tRC tRC
(BL = 8, CL = 3)
RAS
tRAS tRP tRAS tRP tRAS tRP
CAS WE BA0/BA1 A10 A0-A9, A11 DQM CKE DQ Bank A Bank B Active Read Precharge Active Read
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QA a6 QB b0 QBb1 QBb4 QB b5 QB b6 QBb7 QAc0 QAc1 Bank tRCD RAa RAa RB b RBb Bank Bank Bank tRCD RAc Bank Bank Bank tRCD Bank Bank
CAa
CBb
RAc
CAc
Precharge
Active
Read Precharge
BA0 and BA1 together determine which bank undergoes operations.
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ALLIANCE SEMICONDUCTOR
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AS4LC4M16S0 AS4LC16M4S0
(R)
Interleaved bank read waveform
CLK
tRC
(BL = 8, CL = 3, Autoprecharge)
CS
tRC
RAS
tRAS tRP tRAS tRAS tRP
CAS WE BA0/BA1 A10 A0-A9, A11 DQM CKE DQ Bank A Active Bank B
tRRD QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBb0 QBb1 QBb4 QB b5 QBb6 QAc0 QAc0 Bank tRCD RAa RBb CAa RBb CAb Bank Bank tRCD RAc RAc CAc Bank Bank tRCD Bank
RAa
Read
Active
AP Read
tRRD
Active
Read
AP
BA0 and BA1 together determine which bank undergoes operations. AP = internal precharge begins.
Interleaved bank write waveform
CLK CS
tRC
(BL = 8)
RAS
tRAS tRP tRAS
CAS
tRCD tRCD tRCD
WE BA0/BA1 A10 A0-A9,A11 DQM CKE DQ Bank A Active Bank B
DAa0 DAa1 DAa4 DAa5 DAa6 DAa7 DBb0 DB b1 DB b2 DBb3 DBb4 DBb5 DBb6 DBb7 DAc0 DAc1 DAc2 Bank Bank Bank Bank Bank Bank
RAa
RBb CAa RBb CAb
RAc RAc CAc
RAa
Write
Active
Write
Precharge
Active
Write Precharge
BA0 and BA1 together determine which bank undergoes operations.
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ALLIANCE SEMICONDUCTOR
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(R)
AS4LC8M8S0 AS4LC4M16S0
(BL = 8, Autoprecharge)
Interleaved bank write waveform
CLK CS
tRC
RAS
tRAS tRP tRAS tRAS
CAS WE
tRCD tRCD Bank Bank RB b RBb Bank Bank Bank RAc RAc tRCD
BA0/BA1 A10 A0-A9.A11 DQM CKE DQ
Bank RAa
RAa
CAa
CAb
CAc
DAa0
DAa1
DAa4 DAa5 DAa6 DAa7
DBb0 DBb1 DBb2 DBb3
DBb4
DBb5 DB b6 DBb7 DA c0 DAc1
DAc2
Bank A Active Bank B
Write Active
AP Bank A Write
Active
Write AP Bank B
BA0 and BA1 together determine which bank undergoes operations. AP = internal precharge begins
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ALLIANCE SEMICONDUCTOR
23
AS4LC4M16S0 AS4LC16M4S0
(R)
Package dimensions
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
c
54-pin TSOP II Min (mm) A - Max (mm)
1.2 - 1.05 0.45
0.21
54-pin TSOP II
E He
A1 A2
b c D l E e
0.05 0.95
0.30 0.12 22.12 10.03
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
D
22.32
10.29
0.80 (typical)
11.56 11.96 0.60
A A1 b e
A2 0-5
He
l
0.40
AC test conditions
- Input reference levels of VIH = 2.0V and VIL = 0.8V - Output reference levels = 1.4V - Input rise and fall times: 2 ns
+1.4V Z0 = 50W 50W CLOAD = 50 pF Figure A: Equivalent output load
DOUT
Ordering information
Part TSOP II, 400 mil, 54-pin TSOP II, 400 mil, 54-pin
-75
AS4LC8M8S0-75TC AS4LC4M16S0-75TC
-8 AS4LC8M8S0-8TC AS4LC4M16S0-8TC
-10 AS4LC8M8S0-10TC AS4LC4M16S0-10TC
-10F AS4LC8M8S0-10FTC AS4LC4M16S0-10FTC
Part numbering system
AS4 DRAM prefix LC LC = 3.3V CMOS XXXS0 Device number for synchronous DRAM -XX 1/frequency T Package (device dependent): TSOP II 400 mil, 54 pin C Commercial temperature range, 0 C to 70 C
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ALLIANCE SEMICONDUCTOR
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